Signal drivers are often formed of scores of transistors connected in parallel. These parallel transistors have their source contacts electrically interconnected and their drain contacts electrically interconnected. The parallel transistors share a gate electrode. At high operating frequencies, the resistance of the gate (Rg) of the transistors becomes problematic because the resistance is relatively large for the scale and establishes an RC (resistance-capacitance) time constant with nearby capacitances, including parasitic capacitances, forming timing delays for the signal. An exemplary current technique, as shown in FIG. 5, places many transistors in parallel and shortens the length of polysilicon from the contact to the end of the channel, lowering the total value of Rg. In FIG. 5, the gate signal input line 70 or branch thereof terminates with a relatively large poly contact pad 72 in proximity to the multiple transistors. The gate electrode common to the transistors has a relatively large pad 54 at one end that overlaps the gate signal line pad 72 and electrically connects to it through plugs 62.
Current techniques have four disadvantages. 1) Current techniques require routing the polysilicon gate electrode outside the active area introducing extra resistance which makes Rg larger. 2) Current techniques allow for a standard of two or more contacts attached to the large polysilicon pad which sets the contact resistance to a non-optimal value. 3) Signal timing and race conditions become critical when trying to activate hundreds of devices simultaneously. 4) At very high frequencies Rg is still too large even with hundreds of transistors in parallel.
Therefore, it would be desirable to provide a circuit arrangement that overcomes the problems of the prior art.